Over recent years, with the advance of semiconductor manufacturing technology, semiconductor devices (transistors) have been miniaturized and highly integrated, and the number of transistors mounted on semiconductor chips (LSIs) is steadily increasing.
An increase in leakage current of a transistor alone resulting from miniaturization and an increase in the number of transistors mounted on a semiconductor chip cause leakage current (leakage power) of the entire semiconductor chip to tend to increase more and more.
On the other hand, less power consumption is desired for semiconductor chips for applications to battery-driven mobile devices and for energy conservation achievements.
For example, an SRAM (Static Random Access Memory: semiconductor storage device) accounts for a large percentage in a semiconductor chip and therefore, leakage reduction for the SRAM is important to reduce consumed power of the entire semiconductor chip.
In other words, an SRAM is used, for example, as a cache memory of an arithmetic processing unit (processor) and a memory for executing high-speed processing. In such an SRAM, especially, a leakage current of a word line driver is very large and accounts for most of a leakage current of an SRAM macro, for example.
As described above, for example, a leakage current of a word line driver in an SRAM is increasing with miniaturization and high integration of transistors, which is contrary to a recent demand for less power consumption.
In a word line driver of an SRAM, for example, a power supply line of a final stage inverter driving a word line takes long time for charge and discharge due to large parasitic capacitance. Therefore, for example, a voltage of a power supply line of the word line driver is dynamically controlled to reduce consumed power, resulting in a decrease in operation speed.
The present embodiment is applied to an SRAM without limitation and is also applicable to various semiconductor storage devices including, for example, a DRAM (Dynamic Random Access Memory). Further, the present embodiment is widely applicable to various semiconductor devices including, for example, a selection/non-selection-switchable circuit block.
In this regard, various semiconductor storage devices for reducing a leakage current have been proposed.
Patent Document 1: Japanese Laid-open Patent Publication No. 2008-521157
Patent Document 2: Japanese Laid-open Patent Publication No. 2001-176270
Patent Document 3: Japanese Laid-open Patent Publication No. H08-234877